Day1 (Oct. 22)

8:00 Registration
8:30-8:40 Opening
8:40-9:20 Keynote
Impact of STT-MRAM and MTJ/CMOS Hybrid NV-Logic
- from NV-MPU to NV-AI Chip -

Tetsuo Endoh, Tohoku University
9:20-10:35 S1: MRAM 1
Chair : Tetsuo Endoh, Tohoku University
9:20-9:45 Towards high density STT-MRAM at sub-20nm nodes
Steven Lequeux, Spintech/CEA-CNRS-UGA
9:45-10:10 Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system
Ryo Tamura, Advantest Corp.
10:10-10:35 Micromagnetic Study of Probabilistic Switching Behavior in Sub 20 nm-CoFeB/MgO Magnetic Tunnel Junction
Chikako Yoshida, Fujitsu Limited
10:35-10:50 BREAK
10:50-12:30 S2: RRAM
Chair : Scott Sills, Micron
10:50-11:15 ReRAM as a highly-reliable embedded memory and its potential for “beyond memory” applications
Ryutaro Yasuhara, Panasonic Semiconductor Solutions
11:15-11:40 What will come after V-NAND - Vertical ReRAM?
Cheol Seong Hwang, Seoul National University
11:40-12:05 A Unified Picture of Resistance Memory and Memristor: From Filamentary to Nanometallic
I-Wei Chen, University of Pennsylvania
12:05-1:15 LUNCH at "HERMITAGE" 3rd floor of the Westin Sendai
1:15-3:20 S3: FeRAM
Chair : Daisaburo Takashima, Toshiba Memory
1:15-1:40 Embedded FeFETs as a low power and non-volatile beyond-von-Neumann memory solution
Sven Beyer, Global Foundries
1:40-2:05 Effects of Interfaces and Electrode Materials on Ferroelectric Resistive Switching Characteristics
Akihito Sawa, National Institute of Advanced Industrial Science & Technology
2:05-2:30 Reliability of HfO2-based Ferroelectric Tunnel Junction Memory
Marina Yamaguchi, Toshiba Memory
2:30-2:55 Fully-Coupled Technology Computer Aided Design Simulation in Negative Capacitance FETs
Hiroyuki Ota, National Institute of Advanced Industrial Science & Technology
2:55-3:20 Capacitor and Tunnel Junction Based Memories Utilizing Ferroelectricity and Antiferroelectricity in Hafnium Oxide
Thomas Mikolajick, TU Dresden
3:20-3:35 BREAK
3:35-5:15 S4: MRAM 2
Chair : Tetsuo Endoh, Tohoku University
3:35-4:00 Advanced Nanoscale Magnetic Tunnel Junctions for Low Power Computing
Weisheng Zhao, Beihang University
4:00-4:25 Design of an MTJ-Based Nonvolatile Logic LSI and Its Application
Takahiro Hanyu, Tohoku University
4:25-4:50 Field-Free Spin-orbit Torque Switching of Perpendicular Magnetic Tunnel Junctions Utilizing Optimized Voltage-Controlled Magnetic Anisotropy
Zong-You Luo, National Taiwan University
4:50-5:15 Smart Gate Driver ICs with Embedded Microprocessor for Precision Control of Modern Power Transistors
Wai Tung Ng, University of Toronto
5:45-7:15 Poster Session at "SUZUME" 2nd floor of the Westin Sendai
[Note] Meal and beverage will be provided.