CIES Consortium

National Projects

JSPS Core-to-Core Program

Controlled Interfacing of 2D materials for Integrated Device Technology

The main research objectives in this program are the development of manufacturing technologies with high-level repeatability for 2D electronic materials using CVD technologies, high-quality 2D electron/spin channel with high quality interface, and theoretical/experimental investigation of 2D electron/spin transport in the channel, with the close collaboration among CIES at Tohoku University, University of Cambridge, CNRS/University of Paris Sud (three core institutes), Engineering Department at Tohoku University, University of Tokyo, University of Tsukuba and Hitach Cambridge Laboratory. In addition to creating the breakthrough technologies for the next-generation semiconductor integrated devices, with the collaboration among the above world-class research institute. This program also concentrates on fostering young researchers who develop the next generation semiconductor technologies.

• JSPS Core to Core