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CIES Consortium
Industry-Academic Collaboration
CIES Consortium
Industry-Academic Collaboration
Project leader: Prof. T. Endoh
LSIs
(Device manufacturing technology)
R&D of STT-MRAM aimed at developing non-volatile working memory and its manufacturing technologies
R&D of technologies to automacally design environments for low-energy consumption and highly functional VLSI processors based on non-volatile memory
Embedded device technology
R&D of supersensitive magnetic sensors using ferromagnetic tunnel junctions
R&D of ultra-small full-spin 3-D wireless semiconductor embedded substrate (SESUB) technologies featuring power saving
System technology
Basic research on image processing technology for next-generation automobiles and information appliances
Research and development on embedded security technology
R&D of a VLSI platform for real-world intelligent integrated systems
Industry-Academic Collaboration
STT-MRAM and its manufacturing process technologies
Automatic design for non-volatile LSI
Supersensitive magnetic sensors
3D wireless SESUB
2D/3D integrated image processing
Embedded security system
Real-world intelligent system
National Projects
Community-based Cooperation Projects
CIES Joint Research
Tohoku University,
Center for Innovative Integrated Electronic Systems
468-1 Aramaki Aza Aoba,
Aoba-ku, Sendai, Miyagi
980-0845, JAPAN
TEL +81-22-796-3410
FAX +81-22-796-3432
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